Hechen Wang

About

Research topics: 1. Compute-in-Memory (CiM), analog/mixed-signal/probabilistic computing for edge artificial intelligence. 2. Digital frequency synthesizer circuits, data converter, Time-to-Digital Converters (TDC), and DTC. 3. Energy-efficient polar wireline, wireless transceiver architecture and direct modulation schemes. 4. Self-powered self-organized wireless sensor network and integrated energy harvesters for IoT.

Work

Intel Corp

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Research Scientist

US

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Education

Auburn University

United States of America
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Ph.D

Auburn University

United States of America
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MS

University of Electronic Science and Technology of China

China
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BS

Publications

Enhancing AI Acceleration: A Calibration-Free, PVT-Robust Analog Compute-in-Memory Macro With Activation Functions

IEEE Solid-State Circuits Letters

journal-article

Analog chip paves the way for sustainable AI

Nature

journal-article

A Charge Domain SRAM Compute-in-Memory Macro With C-2C Ladder-Based 8-Bit MAC Unit in 22-nm FinFET Process for Edge Inference

IEEE Journal of Solid-State Circuits

journal-article

A Charge Domain SRAM Compute-in-Memory Macro With C-2C Ladder-Based 8-Bit MAC Unit in 22-nm FinFET Process for Edge Inference

IEEE Journal of Solid-State Circuits

journal-article

An Energy-Efficient Bayesian Neural Network Accelerator With CiM and a Time-Interleaved Hadamard Digital GRNG Using 22-nm FinFET

IEEE Journal of Solid-State Circuits

journal-article

Energy Efficient BNN Accelerator using CiM and a Time-Interleaved Hadamard Digital GRNG in 22nm CMOS

2022 IEEE Asian Solid-State Circuits Conference (A-SSCC)

conference-paper

A 32.2 TOPS/W SRAM Compute-in-Memory Macro Employing a Linear 8-bit C-2C Ladder for Charge Domain Computation in 22nm for Edge Inference

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

conference-paper

A Digital Root Based Modular Reduction Technique for Power Efficient, Fault Tolerance in FPGAs

2020 30th International Conference on Field-Programmable Logic and Applications (FPL)

conference-paper

A Digital Root Based Modular Reduction Technique for Power Efficient, Fault Tolerance in FPGAs

Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)

journal-article

Sub-Sampling Direct RF-to-Digital Converter With 1024-APSK Modulation for High Throughput Polar Receiver

IEEE Journal of Solid-State Circuits

journal-article

Sub-Sampling Direct RF-to-Digital Converter With 1024-APSK Modulation for High Throughput Polar Receiver

IEEE Journal of Solid-State Circuits

journal-article

Time-to-digital converters

Phase-locked Frequency Generation and Clocking

journal-article

A 3.8 mW Sub-Sampling Direct RF-to-Digital Converter for Polar Receiver Achieving 1.94 Gb/s Data Rate with 1024-APSK Modulation

2019 Symposium on VLSI Circuits

conference-paper

A 3.8 mW Sub-Sampling Direct RF-to-Digital Converter for Polar Receiver Achieving 1.94 Gb/s Data Rate with 1024-APSK Modulation

Symposium on VLSI Circuits

conference-paper

An 8-bit 80-MS/s Fully Self-Timed SAR ADC with 3/2 Interleaved Comparators and High-Order PVT Stabilized HBT Bandgap Reference

2019 IEEE International Symposium on Circuits and Systems (ISCAS)

conference-paper

An 8-bit 80-MS/s Fully Self-timed SAR ADC with 3/2 Interleaved Comparators and High-Order PVT Stabilized HBT Bandgap Reference

IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS

journal-article

A 280MS/s 12b SAR-Assisted Hybrid ADC with Time Domain Sub-Range Quantizer in 45nm CMOS

IEEE Custom Integrated Circuits Conference (CICC)

conference-paper

A bidirectional lens-free digital-bits-in/-out 0.57mm2 terahertz nano-radio in CMOS with 49.3mW Peak power consumption supporting 50cm Internet-of-Things communication

2018 IEEE Custom Integrated Circuits Conference (CICC)

conference-paper

A Reconfigurable Vernier Time-to-Digital Converter With 2-D Spiral Comparator Array and Second-Order $\Delta \Sigma$ Linearization

IEEE Journal of Solid-State Circuits

journal-article

A Reconfigurable Vernier Time-to-Digital Converter With 2-D Spiral Comparator Array and Second-Order $\Delta \Sigma$ Linearization

IEEE Journal of Solid-State Circuits

journal-article

A Reconfigurable Vernier Time-to-Digital Converter With 2-D Spiral Comparator Array and Second-Order Delta Sigma Linearization

IEEE Journal of Solid-State Circuits

journal-article

A Bidirectional Lens-Free Digital-Bits-In/-Out 0.57mm(2) Terahertz Nano-Radio in CMOS with 49.3mW Peak Power Consumption Supporting 50cm Internet-of-Things Communication

IEEE Custom Integrated Circuits Conference (CICC)

conference-paper

A Quadrature VCO with Phase Noise Optimization for Wide Tuning Triple Band Frequency Generation

ArXiv

journal-article

A 14-Bit, 1-ps resolution, two-step ring and 2D Vernier TDC in 130nm CMOS technology

ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference

conference-paper

A 14-Bit, 1-ps Resolution, Two-Step Ring and 2D Vernier TDC in 130nm CMOS Technology

European Solid-State Circuits Conference (ESSCIRC)

conference-paper

An 802.11a/b/g/n Digital Fractional- $N$ PLL With Automatic TDC Linearity Calibration for Spur Cancellation

IEEE Journal of Solid-State Circuits

journal-article

An 802.11a/b/g/n Digital Fractional-N PLL With Automatic TDC Linearity Calibration for Spur Cancellation

IEEE Journal of Solid-State Circuits

journal-article

A 330μW 1.25ps 400fs-INL vernier time-to-digital converter with 2D reconfigurable spiral arbiter array and 2nd-order ΔΣ linearization

2017 IEEE Custom Integrated Circuits Conference (CICC)

conference-paper

A bidirectional lens-free digital-bits-in/-out 0.57mm2 Terahertz nano-radio in CMOS with 49.3mW peak power consumption supporting 50cm Internet-of-Things communication

2017 IEEE Custom Integrated Circuits Conference (CICC)

conference-paper

A 330 mu W 1.25ps 400fs-INL Vernier Time-to-Digital Converter with 2D Reconfigurable Spiral Arbiter Array and 2nd-Order Delta Sigma Linearization

IEEE Custom Integrated Circuits Conference (CICC)

conference-paper

An 802.11 a/b/g/n digital fractional-N PLL with automatic TDC linearity calibration for spur cancellation

2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

conference-paper

An 802.11 a/b/g/n Digital Fractional-N PLL with Automatic TDC Linearity Calibration for Spur Cancellation

Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium

conference-paper

A wide tuning triple-band frequency generator MMIC in 0.18μm SiGe BiCMOS technology

2014 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)

conference-paper

A Wide Tuning Triple-Band Frequency Generator MMIC in 0.18μm SiGe BiCMOS Technology

IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)

conference-paper